Solid state digital storage apparatus

ABSTRACT

A signal voltage source exhibiting a digital waveform is connected in series with a DC bias voltage source and the combination is placed across the anode and cathode of a bulk semiconductor which exhibits the phenomenon of domain propagation. Pairs of contacts are placed along the surface of the device such that when a propagating domain is between a specified set of contacts, the voltage measured across these contacts is directly related to the digital signal applied across the device. The potential drop across contact pairs is in turn used to control memory devices which store the digital signal.

United States Patent Inventor Richard B. Robrock, ll

Matawan Township, Monmouth County, NJ.

Appl. No. 838,178

Filed July I, 1969 Patented June 15, 1971 Assignee Bell Telephone Laboratories, Incorporated Murray Hill, Berkeley Heights, N .J.

SOLID STATE DIGITAL STORAGE APPARATUS 2 Claims, 2 Drawing Figs.

[56] References Cited UNITED STATES PATENTS 3,320,596 5/1967 Smith Primary Examiner-Terrell W. Fears Attorneys-R. J. Guenther and E. W. Adams, Jr.

US. Cl 340/173,- between a specified set of contacts, the voltage measured 307/238, 307/308 across these contacts is directly related to the digital signal ap- Int. Cl ..t Gllc 11/34 plied across the device. The potential drop across contact Field of Search 307/308, pairs is in turn used to control memory devices which store the 238; 340/173, 173.2, 173 MS, 173 SS digital signal.

T 22 a 37 1 38 -39 SOllCE TRIGGER 3 B PULSES 35 1' :1 1'3 SYNC. 3

z l-M A soun STATE DIGITAL STORAGE APPARATUS BACKGROUND OF THE INVENTION This invention relates to circuit arrangements which employ as the active device a bulk semiconductor which exhibits the phenomenon of domain nucleation and propagation. The mechanism for this observed phenomenon is believed to result from thecarriers in such materials exhibiting negative incremental mobility'over a range of applied electric field. The source of this negative incremental mobility is vastly different from one material'to the next. In gold-doped Ge it may be attributed to afield-dependent trapping effect, in CdS to phonon-electron interaction, while in GaAs, lnP, CdTe, ZnSe and others it is believed to be the result of an intervalley scattering mechanism. The basic theory of these devices is set forth in detail in a series of papers in the Jan. 1966 IEEE, Transactions on Electron Devices, Volume ED-l3, No. l, and Sept. I967 IEEE, Transactions on- Electron Devices, Volume ED-l4, No.9.

As set forth-inthe papers mentioned above, when an increasing voltage is applied to opposite endsof a suitable sample of a bulk semiconductor, such as N-type gallium arsenide,

the average current in the sample increases almost linearly with voltage until a'critical value is reached, at which point the current drops sharplyto a fraction of its maximum value. Above this critical voltage the average current in the sample remains essentially constant. In addition, in' this range of reduced current the instantaneous waveform is found to con tain coherent oscillations at a frequency related to the sample length. The'critical voltage at which the drop incurrent in the sample takes place and at which oscillations are initiated is termed the threshold voltage, V v

Present theory holds that these oscillations result from the nucleation of domains in a region near the negative electrode (cathode) and the propagation of these domains towards the positive electrode (anode). Following the nucleation phase, a domain grows to a stable shape andcontinues to drift towards the positive electrode, even if the applied voltage is lowered, as long as this voltage remains above a minimum value which is termed the domain sustaining voltage, V If the applied voltage exceeds a value known as the oscillation sustaining voltage, V thenthearrival of a domain at theanode results in the nucleation of a new domainxnear the cathode, and the continued nucleation, propagation and dissolution of domains produces coherent oscillations in the observed current waveform. 0n the other hand, if the applied voltage is less than V but greater than V,, then the dissolution of a domain at theanode returns the device to its original ohmic state.

It has been found that in addition to initiating domain nucleation by means of a voltage applied across the anode and cathode of a bulk semiconductor device, it is also possible to cause domain nucleation through the application of a positive potential to a third terminal of the device, physically located between theanode and .the cathode. This third terminal may be a simple ohmic contact in which metal is physically bonded to the semiconductor structure, or it may be a capacitive contact where themetallization is isolated from the semiconductor by an insulating layer. In this latter type of contact the signals applied to the third input terminal are inherently capacitively coupled to the semiconductor device. It has been found that, regardless of the type of bonding employed in the third terminal, relatively low voltages are required at such a terminal to initiate domain nucleation, even where the voltage between the anode and cathode issubstantially below the threshold voltage, V-,. The apparent reason for this phenomenon is that a voltage applied to the third terminal need only increase the electric field over threshold in the region between this terminal and the cathode.

SUMMARY OF THE INVENTION In accordance with this invention, a signal voltage consisting of a digital waveform is placed in series with a source of DC bias voltage and the combination is connected across the anode and cathode of a bulk semiconductor device in which domains are nucleated by the application of a trigger pulse to a third input terminal located in close proximity to the cathode. Additional pairs of contactsare provided across the surface of the device between the third input terminal and the anode, and it has been found that as a domain passes between each pair of contacts a voltage is generated across the pair in accordance with the voltage of the digital signal at that time. The voltages generated at these pairs of contacts arefurther used to control memory devices so as to store the digital signal.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 shows a bulk device serial input digital store embodying the present invention; and

FIG. 2 shows the time relationship between the pulse which triggers a domain and the information signal.

DETAILED DESCRIPTION 7 A source of digital signals 10 is placed in series with a source of bias voltage 11 and connected across the anode l2 and cathode 13 of a bulk semiconductor body 14. The

semiconductor body 14 may comprise bulk gallium arsenide or any one of several materials .exhibiting the phenomenon of domain nucleation and propagation. The voltage provided by sources- 10 and 11 is arranged. to provide a bias across the semiconductor body which always exceeds the domain sustaining voltage, V but during domain dissolution does not exceed the oscillation sustaining voltage V,,;. Thus, when a short input trigger pulse from source 22 causes a domain to be nucleated in the device 14, that domain willpersist until it reaches the positive contact, or anode l2, whereupon the device will return to its ohmic state.

The signals from source 10 are digital signals which may be received from any one of a variety of sources providing digital information-in serial form and which are intended to be stored in some form of voltage sensitive-storage apparatus.

It is known that the mechanism of domain propagation in bulk semiconductors permits relatively instantaneous control of the excess voltage of a traveling domain by varying the external bias applied to the semiconductor body. In this regard an increment AV in the applied bias voltage across the anode 12 and cathode 13 results in an increment AV in the domain excess voltage which is greater than or equal to AV. In accordance with this invention, this phenomenon is utilized to generate domain voltages corresponding to the digital voltage waveform. The digital signal from source 10 is correlated with the velocity of domain propagation and the position of the contact pairs along the semiconductor body 14. Additionally,

the trigger pulse from source 22 is correlated with the digital waveform from source 10 so that each bit of the serial digital signal is received at a time when the domain is passing between the appropriate pair of contacts along the surface of device 14. To accomplish this result, sources 10 and 22 may be interconnected by a synchronizing circuit 15 which is usually part of the associated digital apparatus and serves to provide an enabling voltage to the trigger circuit at a predetermined time prior to the generation of a digital signal by source 10. An illustrative time relationship between the trigger pulse and the information signal is shown in FIG. 2.

Contacts 25 and 26 comprise the first pair of contacts, contacts 27 and 28 comprise the second such pair and contacts 29 and 30 comprise the third such pair. If a positive pulse is present in the received digital signal from source 10 at a time when a domain is passing between the contacts comprising a pair then the voltage difference between those two contacts is sufficient to trigger a storage element into the one state. For example, if a pulse is present at digital source when the domain passes between contacts 25 and 26 then the voltage difference between these contacts when applied to the capacitive contacts 35 and 36 on semiconductor body 37 is sufficient to nucleate a domain in that device so that it functions either as a monostable multivibrator or it continues to oscillate and functions as a bistable multivibrator so that a permanent memory is achieved. The latter operation is disclosed in copending application Ser. No. 542,168 filed by M. Uenohara on Apr. 12, 1966. On the other hand, if no pulse is present in the received signal from source 10, then the propagating domain does not contain a sufficiently large excess voltage as measured between contacts 25 and 26 to trigger a domain in device 37 so that the device remains in the zero" or ohmic state. Thus, if a digital signal is supplied by source 10 and synchronized with the trigger pulse 22 so that each bit of the digital signal occurs when the domain is passing between a pair of contacts then the apparatus shown in the drawing is capable of storing any binary word present in the digital signal.

As above stated, in order to achieve complete storage of the digital signal each pair of contacts has associated with it a bulk semiconductor device 37, 38 and 39 which is capable of being triggered to either nucleate a domain and function as a monostable pulse source or to continue in oscillation upon the nucleation of a domain in the manner described in the abovementioned patent application so that the digital signal from source 10 is permanently stored in the semiconductor devices 37, 38 and 39. In this regard it is necessary that the storage elements 37, 38 and 39 be designed such that domains can only be nucleated in the region between the capacitive contact pairs. For example, the nucleation of a domain in device 14 causes an immediate increase in the potential at contact 25. This increase is coupled to contact 36 on the storage element 37, and care must therefore be exercised so that a domain is not erroneously nucleated between contact 36 and the cathode of device 37. Similarly, when a domain passes contact 26 an immediate drop in potential is coupled to contact 35 and thus device 37 must be designed such that in this situation a domain is not generated between contact 35 and the anode of the device. Finally, care must be taken to insure that the passage of a domain between contacts 36 and 35 does not result in the nucleation of a domain between contacts 25 and 26 in the main device. To meet these requirements it may be desirable to add attenuation between electrodes 25, 26 and 36, 37. The required attenuator may take the form of a capacitive divider.

Various embodiments and modifications other than those described herein may be made by those skilled in the art without departing from the spirit and scope of the invention. In this regard contacts 25, 26, 27, 28, 29, 30 may be capacitive while 35, 36, etc., are ohmic. In addition it is possible to share contacts on the main device 14 among the storage elements 37, 38, 39. For example, contacts 26 and 27 may become a single electrode as may contacts 28 and 29.

I claim:

1. A serial input digital store comprising, in combination, a bulk semiconductor device having an anode, a cathode, and a third electrode, pairs of contacts bonded to said semiconductor device between said anode and said cathode, a source of bias voltage, a source of serial digital signals, means connecting said bias source and said digital signal source in series between said anode and said cathode, a memory element connected to each pair of contacts, a source of trigger pulses connected to said third terminal so that domains are nucleated in said device, and means to synchronize said digital signal to said trigger pulses so that the voltage across a predetermined pair of contacts is representative of the state of the digital signal at that time.

2. A serial input digital store comprising, in combination, a

bulk semiconductor device having an anode, a cathode, and a third electrode, pairs of ohmic contacts connected to said semiconductor material between said anode and said third electrode, a source of bias voltage, a source of serial digital signals, means connecting said bias and said digital signal sources in series between said anode and cathode, a memory element comprising a bulk semiconductor device having an anode and a cathode and two capacitive contacts bonded to its surface, said capacitive contacts each being connected to one of a pair of said ohmic contacts on said first semiconductor device, a source of trigger pulses connected to said third terminal of said first semiconductor device so that domains are nucleated in said device, means to synchronize said digital signal to said trigger pulses so that the voltage across a specified pair of contacts is representative of the state of the digital signal at that time, and means to bias each of said second semiconductor devices so that a domain is nucleated therein when the digital signal contains a positive pulse at the time said domain in the main device passes between the appropriate pair of contacts. 

1. A serial input digital store comprising, in combination, a bulk semiconductor device having an anode, a cathode, and a third electrode, pairs of contacts bonded to said semiconductor device between said anode and said cathode, a source of bias voltage, a source of serial digital signals, means connecting said bias source and said digital signal source in series between said anode and said cathode, a memory element connected to each pair of contacts, a source of trigger pulses connected to said third terminal so that domains are nucleated in said device, and means to synchronize said digital signal to said trigger pulses so that the voltage across a predetermined pair of contacts is representative of the state of the digital signal at that time.
 2. A serial input digital store comprising, in combination, a bulk semiconductor device having an anode, a cathode, and a third electrode, pairs of ohmic contacts connected to said semiconductor material between said anode and said third electrode, a source of bias voltage, a source of serial digital signals, means connecting said bias and said digital signal sources in series between said anode and cathode, a memory element comprising a bulk semiconductor device having an anode and a cathode and two capacitive contacts bonded to its surface, said capacitive contacts each being connected to one of a pair of said ohmic contacts on said first semiconductor device, a source of trigger pulses connected to said third terminal of said first semiconductor device so that domains are nucleated in said device, means to synchronize said digital signal to said trigger pulses so that the voltage across a specified pair of contacts is representative of the state of the digital signal at that time, and means to bias each of said second semiconductor devices so that a domain is nucleated therein when the digital signal contains a positive pulse at the time said domain in the main device passes between the appropriate pair of contacts. 